Embodiments of the inventive concepts described herein relate to integrated circuits and design methods of the integrated circuits, and more particularly, relate to integrated circuits including cells arranged considering a supply voltage variation of cells and influence between the cells, and design methods of the integrated circuits.
A static timing analysis (STA) may be used when designing an integrated circuit such as a system on chip (SoC), an application specific integrated circuit (ASIC), a memory, or the like. The static timing analysis may include the process of calculating delays of cells in the integrated circuit and determining whether a timing violation (e.g., a setup timing violation or a hold timing violation of a flip-flop) may occur.
Due to process miniaturization, a width of a line in the integrated circuit may become narrow, and an operation voltage of the integrated circuit may decrease. Also, influence between cells in the integrated circuit may increase. A dynamic voltage variation that can occur due to influences between resistances of lines for transmitting power and/or due to influences between cells may have impacts on the operation of the integrated circuit which may reduce performance and/or yield.